1. Field of the Invention
The present invention relates to data transmission between a master and a slave.
2. Description of the Prior Art
Conventionally, data transmission has been widely conducted between a master and a slave, using a system controller such as a microcomputer as a master and various circumferencial ICs such as a display LSI, a PLL-LSI, a graphic equalizer LS2, and an electronic volume LSI as a slave.
Japanese Patent Publication No. Hei 3-31298 (JP-B-03031298), for instance, discloses a technique in which one master and a plurality of slaves are connected via four serial lines so that clock CL, control signal CE, input data SI, and output data SO are transmitted via the lines. When input data is transmitted from a master to a slave in this invention, a master first renders a control signal CE to be at L-level and then outputs a clock to a clock line and a first address code unique to each slave to a data SI line. Following this, the master changes the control signal CE to be at H-level and outputs a clock to the clock line and input data to the data SI line. A slave receives the address code which has been transmitted with a L-level control signal CE in synchronism with the clock CL via its address register. The slave then judges whether the received address coincides with the first address assigned to itself. If it does, the slave incorporates the input data which has been transmitted with an H-level control signal CE into its data register. Responding to the control signal CE changing from H-level to L-level (a trailing edge of the control signal CE), the slave latches the content of its data register into a latch circuit.
In contrary cases, that is, in cases where data is transmitted from a slave to a master, a master first renders a control signal CE to be at L-level and outputs a clock to a clock line and a second address which is different from the first address code to a data SI line. Following this, the master changes the control signal CE into H-level and outputs solely a clock to the clock line. A slave receives the address code which has been transmitted with an L-level control signal CE in synchronism with the clock CL via its address register. The slave then judges whether the received address coincides with the second address which has been assigned to itself. If it does, the slave outputs the content of the output data register which is incorporated therein to the data SO line while a control signal CE remains at H-level.
The aforementioned data transmission method is advantageous in that it can use a general serial I/O and imposes only small burden on hardware. In addition to these, the data transmission speed can be increased with low possibility of error operations. This is thus preferable to be used particularly in an audio-related field.
The conventional data transmission method is mechanically satisfactory as described above. However, it requires four serial lines for data transmission from a slave to a master, although three is sufficient for a master-to-slave data transmission. Therefore, for bidirectional data transmission, a master and a slave must be connected via four lines. In general, a fewer number of signal lines are preferable for connection between devices. Thus, the conventional data transmission method has a problem in this respect.
Further, in the conventional method, an input data line is independent from an output data line. This makes it easy to use an output data line to transmit a read request from a slave to a master without problems. However, in cases when the same line is used as input and output data lines, if a read request is once made, an address or data will not be able to be transmitted from a master to a slave thereafter.